1. Field of the Invention
The present invention relates to an overvoltage suppressing circuit for a semiconductor device which is adapted to suppress an overvoltage of a semiconductor switching device used for a power converter or the like.
2. Description of the Related Art
FIG. 7 is a circuit diagram of a chopper circuit having an overvoltage suppressing circuit of a semiconductor device disclosed in "Voltage Clamp Circuit for a Power MOSFET PWM Inverter" IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS Vol. IA-23 No. 5 SEPTEMBER/OCTOBER 1987, pp. 911-920. In the drawing, the chopper circuit comprises a DC power source 1; a transistor 2; a parasitic capacitance 3 between the main circuit terminals of the transistor 2; a reflux diode 4 inserted between the emitter of the transistor 2 and the negative pole of the DC power source 1; a load device 5 connected in parallel with the reflux diode 4; and an overvoltage suppressing circuit 6 for the transistor 2 including an overvoltage suppressing capacitor 61, an oscillation suppressing diode 62, and a discharging resistor 63 for the overvoltage suppressing capacitor 61.
The overvoltage suppressing capacitor 61 and the oscillation suppressing diode 62 are connected in series between the collector and emitter of the transistor 2, while the discharging resistor 63 is connected between the negative pole of the DC power source 1 and a connecting point between the overvoltage suppressing capacitor 61 and the oscillation suppressing diode 62.
In the drawing, reference numeral 7 denotes an inductance of the wiring.
A description will now be given of the operation with reference to a waveform diagram shown in FIG. 8. The transistor 2 being energized is turned off at time T.sub.0.
A voltage V.sub.CE between the main circuit terminals of the transistor 2 rises from time T.sub.0 and reaches a terminal voltage V.sub.D of the DC power source at time T.sub.1. After time T.sub.1, the current i.sub.c of the transistor 2 decreases gradually from a collector DC current Ic. The inductance 7 of the wiring tries to maintain a current i.sub.D flowing from the DC current source 1 at a constant level. Since the current i.sub.D of the DC power source 1 is branched at a Connection point P.sub.1 into the current i.sub.C flowing to the transistor 2 and a current i.sub.S flowing to the overvoltage suppressing circuit 6, the following relationship exists among the currents i.sub.D, i.sub.C and i.sub.S : EQU i.sub.S =i.sub.D -i.sub.C ( 1)
Accordingly, if the current i.sub.D is assumed to be fixed during the period from the time T.sub.1 to the time T.sub.2, as shown in FIG. 8, the current i.sub.S flowing into the overvoltage suppressing circuit 6 increases in accordance with Formula (1) with a decrease in the current flowing through the transistor 2.
The period from time T.sub.2 to time T.sub.3 is a period in which energy accumulated in the inductance 7 of the wiring is absorbed by the capacitor 61. In addition, when the current i.sub.S is reduced to 0 at time T.sub.3, a current flows through the diode 62 in the opposite direction since the diode 62 does not have ideal characteristics, so that the current flowing through the diode 62 is suddenly cut off at time T.sub.4 when the, internal carriers disappear.
For this reason, the current which has been flowing through the diode 62 commutes to the parasitic capacitance 3 of the transistor 2.
After time T.sub.4, since the diode 62 is off, the voltage V.sub.CE of the transistor 2 undergoes damped oscillation, from a maximum voltage V.sub.P of the overvoltage suppressing capacitor 61, due to the parasitic capacitance 3, the inductance 7 of the wiring, and the component of resistance contained in the wiring. In addition, the energy charged in the overvoltage suppressing capacitor 61 from the inductance 7 of the wiring during the period from time T.sub.2 to T.sub.3 is discharged through the discharging resistor 63. Accordingly, a current i.sub.R flowing through the discharging resistor 63 declines after time T.sub.4, as shown in FIG. 8.
Since the conventional overvoltage suppressing circuit for a semiconductor device is arranged as described above, there has been a problem that, due to the phenomenon in which the current passing through the transistor 2 changes suddenly to cause voltage oscillation in the transistor 2 when the diode 62 is turned off so that the electromagnetic noise generated by the apparatus becomes large.